In electronic systems, good clock distribution is very important to the overall performance of the electronic systems in general. Unwanted clock skew and jitter typically result from poor clock distribution and cause problems in the design and operation of the electronic systems. Techniques have been developed using PLLs to mitigate the effect of these problems to manageable levels. Therefore, PLLs are widely used in electronic circuits.
FIG. 1A shows a conventional PLL. The PLL 100 comprises a phase frequency detector (PFD) 110, a filter 120, a voltage controlled oscillator (VCO) 130, and a feedback divider 140. The filter 120 may include a charge pump and a loop filter. The inputs to the PFD 110 comprise a reference clock signal 101 and a feedback clock signal 103. The output of the PFD 110 comprises the frequency and phase of the reference signal 101 relative to the feedback clock signal 103, and is input to the filter 120. The filter 120 integrates this information into a voltage output. The voltage output of the filter 120 is provided to the VCO 130. The VCO 130 converts the output voltage from the filter 120 into an output signal having a corresponding frequency. The output of the VCO 130 is coupled to the feedback divider 140. The feedback divider 140 divides down the frequency of the output signal from the VCO 130, which becomes the feedback clock signal 103. The PFD 110 compares the feedback clock signal 103 with the reference clock signal 101.
FIG. 1B shows another conventional PLL 102. The VCO gain variation is compensated by a compensation circuit 22 with a pre-set input control voltage, VCONTROL. The input control voltage is pre-set by the designer of the circuit.
FIG. 1C illustrates the existing VCO gain compensation graphically. As shown in FIG. 1C, the VCO gain 151 decreases as temperature changes from minus 55° C. to plus 155° C. By applying a compensation current 152 with an opposite trend, the overall VCO gain 153 across temperature variation is reduced.
One disadvantage of conventional technology is the inflexibility of the design. Since a pre-determined voltage level is used, the design is less flexible than it could otherwise be. In addition, the conventional solution described above compensates for VCO gain variation caused only by temperature variation. No compensation for VCO gain variation due to process variation and/or voltage variation is provided.
In a conventional clock domain recovery (CDR) PLL, the PLL gains are determined by one or more of the input data transition density, which may have a 20× variation, the charge pump current, which may have a 1.8× variation, the loop filter gain, which may have a 2× variation, and the VCO gain, which may have a 5× variation. The variations in these parameters may be caused by the mismatches in any one or more of the process variation, the temperature, and the voltage.